Senior / Lead Design Verification Engineer

Senior / Lead Design Verification Engineer

Company: Truechip Solutions Pvt. Ltd.

Role: Manager / Lead – Design Verification

Experience: 10+ Years

Location: Bengaluru / Noida

Industry: Semiconductor / VLSI / ASIC / SoC

Job Overview

Truechip Solutions Pvt. Ltd. is looking for an experienced Senior / Lead Design Verification Engineer with 10+ years of hands-on experience in ASIC/SoC Design Verification.

The ideal candidate will have strong expertise in SystemVerilog, UVM, verification methodologies, coverage closure, and protocol verification, along with the ability to lead verification projects and mentor engineering teams.

Key Responsibilities

• Lead end-to-end functional verification of complex IPs, subsystems, and SoCs.
• Develop and maintain reusable SystemVerilog/UVM-based verification environments.
• Define verification strategies, plans, test scenarios, and regression methodologies.
• Develop test cases, assertions, functional coverage models, and coverage plans.
• Perform verification of industry-standard protocols such as:
• AMBA – AXI / AHB / APB
• PCIe
• USB
• Ethernet
• DDR / LPDDR
• UFS
• CXL
• CHI
• NoC
• Other high-speed / industry-standard protocols
• Drive functional, code, toggle, and assertion coverage closure.
• Debug simulation failures and perform detailed root-cause analysis.
• Collaborate with RTL Design, Architecture, Emulation, Firmware, and Physical Design teams.
• Drive verification sign-off based on defined quality and coverage metrics.
• Review verification environments, test plans, and technical deliverables.
• Mentor junior and mid-level engineers and provide technical guidance.
• Lead technical discussions and contribute to improving verification methodologies and processes.

Required Skills

• 10+ years of experience in ASIC / SoC Design Verification.
• Strong hands-on expertise in SystemVerilog and UVM.
• Good understanding of Object-Oriented Programming (OOP) concepts.
• Strong experience with SystemVerilog Assertions (SVA).
• Expertise in constrained-random verification methodologies.
• Strong knowledge of functional, code, toggle, and assertion coverage.
• Hands-on experience with industry-standard simulation tools such as:
• Synopsys VCS
• Cadence Xcelium
• Siemens Questa
• Strong scripting/programming experience in Python, Perl, Shell, or TCL.
• Excellent debugging, analytical, and problem-solving skills.
• Ability to independently drive verification activities and deliverables.

Preferred Qualifications

• Experience in SoC-level verification and subsystem integration.
• Exposure to Formal Verification methodologies.
• Experience with Emulation platforms such as ZeBu or Veloce.
• Exposure to FPGA prototyping.
• Experience working on complex multi-core SoCs and advanced technology nodes.
• Strong experience in technical leadership and team mentoring.
• Excellent communication and stakeholder management skills.

Educational Qualification

• B.E. / B.Tech / M.E. / M.Tech / M.S. in:
• Electronics Engineering
• Electrical Engineering
• VLSI
• Computer Engineering
• or a related field.

Compensation

Budget: Open / Flexible

The company is open to offering up to a 30% hike on the candidate's last drawn CTC, based on experience, technical expertise, and suitability for the role.

Ideal Candidate Profile

We are looking for a hands-on technical leader who can independently drive complex verification projects, solve challenging verification problems, work closely with cross-functional teams, and contribute to building high-quality verification environments for next-generation ASIC/SoC designs.