Manager / Lead – DFT Engineer

Manager / Lead – DFT Engineer

Company: Truechip Solutions Pvt. Ltd.

Experience: 10+ Years

Location: Bengaluru / Noida

Role: Manager / Lead – DFT Engineering

Job Overview

Truechip Solutions Pvt. Ltd. is looking for an experienced Manager / Lead – DFT Engineer with 10+ years of hands-on experience in Design for Test (DFT) for complex ASIC/SoC designs.

The ideal candidate will have strong expertise in DFT architecture, scan insertion, ATPG, MBIST/LBIST, scan compression, JTAG, fault analysis, and silicon bring-up. The candidate will also be responsible for driving DFT implementation, debugging, technical leadership, and mentoring junior engineers.

Key Responsibilities

• Design and implement DFT architecture for complex ASIC/SoC projects.
• Drive scan insertion, scan compression, MBIST, LBIST, JTAG, and boundary scan implementation.
• Develop, generate, and debug ATPG patterns for stuck-at, transition, and advanced fault models.
• Analyze DFT coverage, fault simulation results, diagnosis, and test quality.
• Debug DFT-related issues across RTL, synthesis, physical design, verification, and test environments.
• Collaborate closely with RTL Design, Physical Design, Verification, Product/Test Engineering, and Silicon Validation teams.
• Support post-silicon validation, silicon bring-up, and production test activities.
• Implement and improve DFT methodologies and best practices across projects.
• Lead DFT activities and provide technical guidance to junior and mid-level engineers.
• Identify and resolve complex DFT implementation and coverage challenges.
• Contribute to project planning, technical reviews, and delivery of DFT milestones.

Required Skills

• 10+ years of hands-on experience in DFT/ASIC testing.
• Strong expertise in:
• Scan & Scan Compression
• ATPG
• MBIST & LBIST
• JTAG / IEEE 1149.1
• Boundary Scan
• Fault Simulation & Diagnosis
• DFT Coverage Analysis
• Hands-on experience with DFT tools such as:
• Synopsys TestMAX / TetraMAX
• Cadence Modus
• Or equivalent industry-standard DFT tools.
• Strong understanding of ASIC/SoC design and implementation flows.
• Good knowledge of RTL, Verilog/SystemVerilog, synthesis, and physical design concepts.
• Experience with fault models, ATPG pattern generation, coverage improvement, and failure analysis.
• Knowledge of low-power DFT techniques and test architectures.
• Strong scripting/programming skills in TCL, Perl, Python, or Shell.
• Excellent debugging, analytical, and problem-solving abilities.
• Strong communication and team collaboration skills.

Preferred Qualifications

• B.E./B.Tech/M.E./M.Tech in Electronics, Electrical Engineering, VLSI, or a related discipline.
• Experience working on advanced technology nodes such as 7nm, 5nm, or 3nm.
• Experience with automotive, networking, AI/ML, HPC, or other complex SoC designs.
• Experience leading DFT teams or mentoring engineers.
• Exposure to silicon bring-up, production test, and post-silicon validation.

Compensation

• Budget: Open / Flexible
• Compensation: Up to 30% hike on the candidate's last drawn CTC, depending on experience, skills, and overall fit.
• Exceptional candidates with strong DFT expertise may be considered based on their profile and current compensation.

Ideal Candidate

We are looking for a technically strong DFT professional who can own DFT activities end-to-end, lead complex projects, solve challenging test-related issues, and mentor engineering teams.